An input signal drives both SN7474 D-type flip-flops, which are positive edge-triggered devices. A low-to-high input signal transition triggers the A flip-flop, while a high-to-low input signal transition triggers the B flip-flop via the SN7404 inverter. Either flip-flop in the high state will cause the output to decrease via the SN7402 NOR gate. This in turn disables the opposite flip-flop from going to the high state. The flip-flop in the high state remains there for one clock period, then it is clocked low. With both flip-flops low, the output increases, enabling the opposite flip-flop to be clocked high one-half clock cycle later. This alternate enabling and disabling action of the flip-flops results in a divide-by- 1 1/2 function. That is, three clock pulses in, produce two evenly spaced clock pulses out. The circuit has no lock-up states and no inherent glitches. Replacing the NOR gate with an SN7400 NAND gate inverts the A, B, and output
signals. By adding simple binary or BCD counters, counting chains, such as divide-by-3, -6, -12, -24, -15, -30, etc., can be generated using the divide-by-1 1/2 circuit as a basis.