Frequency to Voltage Converter
In these applications, a pulse input at Fin is differentiated by a C-R network and the negative-going edge at pin 6 causes the input comparator to trigger the timer circuit. Just as with a V-to-F converter, the average current flowing out of pin 1 is Iaverage = i x (1.1 R1C1) x f. In this simple circuit, this current is filtered in the network RL = 100 k ohm and 1mF. The ripple will be less than 10 mV peak, but the response will be slow, with a 0.1 second time constant, and settling of 0.7 second to 0.1%.
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Click para ampliarLow Frequency Divider
The ratio of capacitors C1 and C2 determines division. With a positive pulse applied to the base of Q1, assume that C1 = C2 and that C1 and C2 are discharged. When Q1 turns off, both C1 and C2 charge to 10 volts each through R3. On the next pulse to the base of Q1, C1 is again discharged but C2 remains charged to 10 volts. As Q1 turns off this time, C1 and C2 again charge. This time C2 charges to the peak point firing voltage of the PUT causing it to fire. This discharges capacitor C2 and allows capacitor C1 to charge to the line voltage. As soon as C2 discharges and C1 charges, the PUT turns off. The next cycle begins with another positive pulse on the base of Q1 which again discharges C1. The input and output frequency can be approximated by the equation
For a 10 kHz input frequency with an amplitude of 3 volts, the table shows the values for C1 and C2 needed to divide by 2 to 11.
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For a 10 kHz input frequency with an amplitude of 3 volts, the table shows the values for C1 and C2 needed to divide by 2 to 11.
Click para ampliarFrequency Doubler Works to 1Mhz
Frequency Doubler
The output contains the sum component, which is twice the frequency of the input, since both input signals are the same frequency.
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Click para ampliarFrequency Divider
If the input frequency is known, the timer can easily be used as a frequency divider by adjusting the length of the timing cycle. Figure shows the waveforms of the timer when used as a divide-by-three circuit. This application makes use of the fact that this circuit cannot be retriggered during the timing cycle.
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Click para ampliarDivide by -1 1/2 Circuit
An input signal drives both SN7474 D-type flip-flops, which are positive edge-triggered devices. A low-to-high input signal transition triggers the A flip-flop, while a high-to-low input signal transition triggers the B flip-flop via the SN7404 inverter. Either flip-flop in the high state will cause the output to decrease via the SN7402 NOR gate. This in turn disables the opposite flip-flop from going to the high state. The flip-flop in the high state remains there for one clock period, then it is clocked low. With both flip-flops low, the output increases, enabling the opposite flip-flop to be clocked high one-half clock cycle later. This alternate enabling and disabling action of the flip-flops results in a divide-by- 1 1/2 function. That is, three clock pulses in, produce two evenly spaced clock pulses out. The circuit has no lock-up states and no inherent glitches. Replacing the NOR gate with an SN7400 NAND gate inverts the A, B, and output
signals. By adding simple binary or BCD counters, counting chains, such as divide-by-3, -6, -12, -24, -15, -30, etc., can be generated using the divide-by-1 1/2 circuit as a basis.
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signals. By adding simple binary or BCD counters, counting chains, such as divide-by-3, -6, -12, -24, -15, -30, etc., can be generated using the divide-by-1 1/2 circuit as a basis.
Click para ampliarBroadband Frequency Doubler
This circuit will double low-level signals with low distortion. The value of C should be chosen for low reactance at the operating frequency. Signal level at the carrier input must be less than 25 mV peak to maintain operation in the linear region of the switching differential amplifier. Levels to 50 mV peak may be used with some distortion of the output waveform.. If a larger input signal is available, a resistive divider may be used at the carrier input with full signal applied to the signal input.
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