Q1 and Q2 constitute a simple, high speed FET input buffer. Q1 functions as a source follower, with the Q2 current source load setting the drain-source channel current. Normally, this open loop configuration would be quite drifty because there is no dc feedback. The LTC1052 contributes this function to stabilize the circuit by comparing the filtered circuit output to a similarly filtered version of the input signal. The amplified difference between these signals is used to set Q2's bias and hence Q1's channel current. This forces Q1's Vgs to whatever voltage is required to match the circuit's input and output potentials. The 2000 pF capacitor at A1 provides stable loop compensation. The RC network in A1's output prevent it from seeing high speed edges coupled through Q2's collector-base junction. A2's output is also fed back to the shield around Q1's gate lead, bootstrapping the circuit's effective input capacitance down to less
than 1 pF. For very fast requirements, the alternate discrete component buffer shown will be useful. Although its output is current limited at 75 mA, the GHz range transistors employed provided exceptionally wide bandwidth, fast slewing and very little delay.