Circuitos de Electronica: Circuitos de Display

Low Frequency Prescaler

For multiplying frequencies in the 1-to 150-Hz range, this circuit uses a 4046B and a divide 100 prescaler. The VCO output is phaselocked to the low-frequency input. This simplifies use of a frequency counter to measure LF signal frequencies. By using a 4017B and a 1-kHz fIN, the circuit can be used as a 1-to 9-kHz frequency synthesizer or as a x10 frequency multiplier.

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10Mhz Frequency Counter

The circuit consists of ICM7208 seven-decade counter U1, ICM7207 oscillator controller U2, and CA3130 BIFET op amp U3. IC U1 counts input signals, decodes them to 7-segment format, and outputs signals that are used to drive a 7-digit display. IC U2 provides the timing for U1, while U3 conditions the input to U1. The 5.24288-MHz crystal frequency is divided by U2 to produce a 1280-MHz multiplexing signal at pin 12 of U2. That signal is input to pin 16 and used to scan the display digits in sequence.

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1.2Ghz Frequency Counter

The output of the CA 3179 is fed through the D1/Q1 circuit. Those components serve to boost the 1-V output of the CA3179 to a standard TTL level. Then, depending on the position of range switch S2b, the signal is passed directly to the 7216, or through the divide-by-four circuit built from the two D flip-flops in IC3.

The other half of the range switch S2a controls the voltage at pin 3 of the CA3179. When pin 3 is high, the signal applied to pin 9 is fed through an extra internal divide-by-four stage before it is amplified and output on pins 4 and 5 . When pin 3 is low, the signal on pin 13 is simply processed for output without being divided internally.

A 3.90625-MHZ crystal provides the time base: the crystal yields gate time of 0.256 second. The displayed frequency equals the input frequency divided by 1000 in the fast mode. In slow mode, gate time is 2.56 seconds. The displayed frequency equals the input frequency divided by 100 in the slow mode.

Switch S4, gate time, performs two functions. First it selects the appropriate gate time according to which digit output of IC1 the range input is connected to. Another of the 7216's inputs is also controlled by S4: the DP select input. The decimal point of the digit output to which that pin is connected will be the one that lights up. The correct decimal point illuminates, according to the position of S4, to provide a reading in MHz.

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Large LCD Display Buffering Driver

Large LCD devices of 1" or more exhibit a large driving capacitance to the driver circuits. To solve this problem, the drive circuit shown (see the figure) introduces a buffer amplifier for each of the three common lines. Each amplifier can be programmed independently for a quiescent current of 10, 100, or 1000uA. In this application, the bias network applies a voltage that sets the three quiescent currents to 100uA.

The display driver and triple op amp operate between 5V and ground, and the COM signals range from 5V to approximately 1V. To ensure that these signals remain within the amplifiers' common-mode range, the signals are attenuated by one-half and the buffers operate at a gain of two. The circuit drives eight 1-inch displays, and is suitable for ambient temperature variations of 15 degrees F or less. At the highest expected temperature, R1 should be adjusted so that no "off" segments are visible.